This invention relates to the field of data processing systems. More particularly, this invention relates to asynchronous bridge circuitry for use in transferring data from source circuitry operating in a source clock domain to destination circuitry operating in a destination clock domain that is not synchronised with respect of the source clock domain.
It is known to provide data processing apparatus, such as system-on-chip integrated circuits, which include multiple asynchronous clock domains. Part of the apparatus will operate under control of a source clock signal and another part of the apparatus will operate under control of a destination clock signal that is asynchronous with source clock signal. When it is desired to pass data (signals) between source circuitry in the source clock domain and destination circuitry in the destination clock domain, then one way of achieving this is to use asynchronous bridge circuitry incorporating a first-in-first-out buffer. The first-in-first-out buffer may be located within the source clock domain and serve to store data which is to be written to the destination circuitry in the destination clock domain. Metastability resolving circuitry and synchronising circuitry may be provided across the clock domain boundary and permit data to be read from the first-in-first-out buffer by the destination circuitry in synchronism with the destination clock.
As the speed of data processing apparatus increases, and the relative time delay in transmitting data from a source to our destination increases compared with the processing speed, it becomes more difficult to control transfer of data across the clock domain boundary while keeping the overhead associated with the circuitry to achieve this relatively low.